1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device transmitting data by using a data strobe signal.
2. Description of the Related Art
In general, semiconductor memory devices such as a dynamic random access memory (DRAM) receive write data from a chip set, for example, a memory controller, and transmit read data to the chip set. In a synchronous memory system, both the chip set and a semiconductor memory device operate in synchronization with a system clock. However, when data are transmitted from the chip set to the semiconductor memory device, the data and the system clock have different traces so that the data and the system clock have different loads. In addition, a skew occurs between the data and the system dock due to a positional difference among a plurality of semiconductor memory devices included in the memory system.
To reduce a skew between the data and the system clock, a data strobe signal DQS is transmitted together with the data when the data is transmitted from the chip set to a semiconductor memory device. The data strobe signal DQS is referred to as an echo clock. The data strobe signal DQS has the same trace as the data, thus a skew occurring due to a positional difference may be minimized since the semiconductor memory device strobes the data based on the data strobe signal DQS. Therefore, the semiconductor memory device transmits a read data strobe signal DQS along with data to the chip set during a read operation.
FIG. 1 is a timing diagram for describing a read operation of a semiconductor memory device.
FIG. 1 shows timing of signals when column address strobe (CAS) latency CL is 2, and a burst length BL is 4. For reference, a CAS latency CL defines the number of clock cycles until data is outputted from a moment when a read command is inputted. Further, a burst length BL defines the number of data which are successively processed, that is, inputted outputted. Additionally, “CLK” denotes a source clock, and “/CLK” denotes a complementary source clock.
As illustrated in FIG. 1, a data strobe signal DQS has a preamble section representing the beginning of data transmission one clock cycle, that is, 1tCK) before a CAS latency CL. The data strobe signal DQS has the preamble section representing the beginning of the data transmission 1tCK before data is actually outputted in response to a read command READ. The preamble section of the data strobe signal DQS may introduce that the arrival of the data is imminent to a memory controller, which receives and processes the data outputted from the semiconductor memory device. For example, the data strobe signal DQS may start toggling from a high impedance Hi-Z state or change to a predetermined logic level, for example, a low logic level, in the preamble section and which is recognized in the memory controller.
To accurately transmit data between a semiconductor memory device and a memory controller, it may be highly important to accurately define a preamble section of a data strobe signal.